Enable=DISABLED_THE_SPI_IS, SPOL=LOW_THE_SSEL_PIN_IS, LSBF=STANDARD_DATA_IS_TR, Loop=DISABLED_, Master=SLAVE_MODE_THE_SPI_, CPOL=LOW_THE_REST_STATE_, CPHA=CHANGE_THE_SPI_CAPT
SPI Configuration register
| Enable | SPI enable. 0 (DISABLED_THE_SPI_IS): Disabled. The SPI is disabled and the internal state machine and counters are reset. 1 (ENABLED_THE_SPI_IS_): Enabled. The SPI is enabled for operation. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| Master | Master mode select. 0 (SLAVE_MODE_THE_SPI_): Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. 1 (MASTER_MODE_THE_SPI): Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. |
| LSBF | LSB First mode enable. 0 (STANDARD_DATA_IS_TR): Standard. Data is transmitted and received in standard MSB first order. 1 (REVERSE_DATA_IS_TRA): Reverse. Data is transmitted and received in reverse order (LSB first). |
| CPHA | Clock Phase select. . 0 (CHANGE_THE_SPI_CAPT): Change. The SPI captures serial data on the first clock transition of the frame (when the clock changes away from the rest state). Data is changed on the following edge. 1 (CAPTURE_THE_SPI_CHA): Capture. The SPI changes serial data on the first clock transition of the frame (when the clock changes away from the rest state). Data is captured on the following edge. |
| CPOL | Clock Polarity select. 0 (LOW_THE_REST_STATE_): Low. The rest state of the clock (between frames) is low. 1 (HIGH_THE_REST_STATE): High. The rest state of the clock (between frames) is high. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| Loop | Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. 0 (DISABLED_): Disabled. 1 (ENABLED_): Enabled. |
| SPOL | SSEL Polarity select. 0 (LOW_THE_SSEL_PIN_IS): Low. The SSEL pin is active low. The value in the SSEL fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL is not inverted relative to the pins. 1 (HIGH_THE_SSEL_PIN_I): High. The SSEL pin is active high. The value in the SSEL fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL is inverted relative to the pins. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |